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MRF89XA
3.8
Data Processing
3.8.2
DATA OPERATION MODES
3.8.1
DATA PROCESSING BLOCK
The MRF89XA has three different data operation
modes which can be selected by the user or
The MRF89XA data processing blocks are as
illustrated in the Figure 3-16 . The role of the data
processing block is to interface the data to/from the
modulator/demodulator and the host microcontroller
access points (SPI, Interrupts (IRQ0 and IRQ1), DATA
pins). It also controls all the configuration registers.
The circuit contains several control blocks which are
described in the following paragraphs.
The MRF89XA implements several data operation
modes, each with their own data path through the data
processing section. Depending on the data operation
mode selected, some control blocks are active while
others remain disabled.
programmer:
? Continuous mode: Each bit transmitted or
received is accessed in real time at the DATA pin.
This mode may be used if adequate external sig-
nal processing is available.
? Buffered mode: Each byte transmitted or received
is stored in a FIFO and accessed through the SPI
bus. The host microcontroller processing over-
head reduced significantly compared to Continu-
ous mode operation. The packet length is
unlimited.
? Packet mode (recommended): User only pro-
vides/retrieves payload bytes to/from the FIFO.
The packet is automatically built with preamble,
Sync word, and optional CRC, DC free encoding
and the reverse operation is performed in recep-
tion. The host microcontroller processing over-
head is further reduced compared to Buffered
mode. The maximum payload length is limited to
the maximum FIFO limit of 64 bytes.
FIGURE 3-16:
TX/RX
MRF89XA DATA PROCESSING BLOCK DIAGRAM
MRF89XA
DATA
Control
IRQ0
IRQ1
Data
RX
SYNC
SPI
TX
Recognition
Packet
Handler
FIFO
(+SR)
CONFIG
DATA
CSDAT
SCK
SDI
SDO
TABLE 3-4:
DATA OPERATION MODE SELECTION
Data Operation Mode
Continuous
Buffered
Packet
? 2010–2011 Microchip Technology Inc.
DMODE1
0
0
1
Preliminary
DMODE0
0
1
x
Register
FTXRXIREG
FTXRXIREG
FTXRXIREG
DS70622C-page 73
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